Here at Pulsonix, we don't believe in reinventing the wheel which is why we've provided a slick (and free of charge) integrated interface to your existing FPGA design tools. Use the tools you know, love and trust, and have the tight integration you have come to expect from Pulsonix.
With both forward and backward annotation of the Part pin data between the FPGA tool and Pulsonix, the transfer of information is error-free and reliable. Total integration at all times is maintained and is driven by a smooth interface.
The Process Flow
FPGA pin assignment data generated by manufacturers' tools can be imported into a part in the Pulsonix library. From there, it can be included with the part into the schematic and propagated forwards to the PCB layout. You can also start from within the Pulsonix Part editor and export the Part pin data to a CSV format file for use with the FPGA tool.
In parallel, you can develop your FPGA internal functionality using the Altera and Xilinx development tools. Once completed, or even part completed, write out an ASCII file. Changes to the FPGA pin out can be quickly reloaded into Pulsonix reducing the need for error prone manual editing.
Reports about pin swaps performed in the Pulsonix PCB will include additional FPGA information to assist with the process of updating the corresponding pin assignments in the FPGA design system.
Multiple FPGA implementations may be retained as separate Parts in the Pulsonix library.
The Pulsonix Part used in the design is then replaced using the new pin mappings to complete the process. This can be an iterative process and run multiple times to completion of the finished FPGA device.
Importing FPGA Pin Data
FPGA pin information can be read into a Pulsonix Part to construct the FPGA pin data using the Import Pin Data option or using Copy/Paste from a spreadsheet.
Additional checks for the Part to gate pin mappings are available by using the Check Pin Mappings option.
Altera PIN file format
The Altera Quartus II software will automatically generate a .pin ASCII format file as Part of the FPGA design process. This file contains pin assignments and other pin information for an FPGA design. Importing a Altera PIN file will assign the Pin Name/Usage values from the file to the Logic Name fields of the Pulsonix Part pins by mapping the Location values from the file to the Pulsonix Part pins' Pin Name fields.
Xilinx PAD file format
A .pad ASCII format file can be generated by the Xilinx ISE software as part of the FPGA design process. This contains the I/O pad assignments and other properties.
CSV file format
Pulsonix FPGA also supports import and export of Part pin data in standard .csv format. When the CSV file includes the Logic Name field the Part will be set as a FPGA.
FPGA Interface Feature Summary:
- Supplied free-of-charge as part of Pulsonix
- Integrated within the Pulsonix design environment
- Supports Industry Standard FPGA design tool Part pin data
- Supported in Pulsonix Schematic and PCB design editors
- Can be used as parallel design process with FPGA tool
- Top-down or bottom-up design process possible
- Start within FPGA design tool
- Start by using Pulsonix Parts
- Easy bi-directional transfer of FPGA data
- Parts used in design marked as 'FPGA' type
- Back annotation data of pin swaps reported
- Supports Altera Quartus II design tool
- Supports Xilinx ISE design tool
- Supports 'generic' CSV format files