Is there a doc that describes the best practice method for doing filled and possibly blind vias for pads on a CSP or BGA package?
I have a WLCSP package that uses 0.40mm pitch on 0.20mm pads and the example layouts from the MFR show lovely filled vias. (I'm assuming as well those are probably laser drilled vias. I haven't yet found an example file that specifies the drill table. :( )
I would advise taking a different approach. The manufacturer of a device like this always recommends nice flat surfaced pads so talk to the board manufacturers direct, obtain knowledge of what they can achieve regarding vias, then decide your design approach. You may well need to consider external layers with laser cut micro-vias.
Are you after a guide in general or how to do it in Pulsonix?
The HDI Handbook is free from this link http://www.hdihandbook.com/index.php and includes some of the IPC-2226 standard in the text. I've only read sections but you may find useful info in here.
The Advanced Technology option for Pulsonix is very good at handling microvias if you've not already got this.
The PCB fabricator will require a separate gerber file that shows which vias you want capped so you could create a new layer class for this with appropriate layers (layer class "CappedVias", layers "Top Capped Vias" and "Bottom Capped Vias") then use the "By Layer" to set up this layer for the pads for the device.
I would put down a normal round pad in the footprint, then in the design use Alt Pad style to switch individual pads over to the pad style that includes a micro-via and the "by layer" setting to have the same pad style/size on the CappedVia layer.
Posted - 06 Oct 2016 : 18:31:00
